1. Field of the Invention:
The present invention relates to a charge transfer device and, particularly, to an improvement of an output stage thereof.
2. Description of the Related Art:
The output of a charge transfer device is taken out through an output stage which converts the value of electric charge into a voltage. FIGS. 1(a)and 1(b) are a plan view of a conventional output stage of the charge transfer device and a sectional view along the line D--D' thereof, and FIGS. 1(c), 1(d) and 1(e) are diagrams of potentials for illustrating the operation of the output stage. To simplify the description, here, the charge transfer device is a surface channel-type charge coupled device, the substrate is a p-type semiconductor substrate, and the carriers to be transferred are electrons. In the drawings, reference numeral 1 denotes a p-type silicon substrate, 2 denotes an insulating film, 3 denotes a transfer channel, reference numerals 4 to 7 denote transfer electrodes composed of a conductor such as polycrystalline silicon or the like, 8 denotes an output gate electrode, 403 denotes a reset gate electrode, and reference numerals 401 and 402 denote an n-type source region and an n-type drain region. A MOS transistor Tr.sub.1 is constituted of 401, 402 and 403. Usually, the charge-to-voltage conversion and the impedance conversion take place in an arrangement composed of the diffused region (floating diffusion layer) 401, an output-stage transistor Tr.sub.2 and a resistor R, and the output appears at a terminal V.sub.OUT. Reference numerals 9 and 10 denote diffusion layers for determining the direction of transfer of electric charge.
Next, operation of the conventional output stage will be described in conjunction with FIGS. 1(c), 1(d) and 1(e). Potentials under the transfer electrodes are changed by changing the clock pulses .phi..sub.1 and .phi..sub.2 to transfer the signal charge toward the right in the drawings. At the same time, a reset pulse .phi..sub.R having a "high" (active) level is produced so that the MOS transistor Tr.sub.1 is turned on. Then, the potential of the floating diffusion layer 401 is reset to be the same as the drain voltage V.sub.RD of the MOS transistor Tr.sub.1 (FIG. 1(c)). Next, in order to detect a signal, the reset pulse .phi..sub.R having "low" level is produced to turn the MOS transistor Tr.sub.1 off, so that a potential barrier is formed under the gate electrode 403 (FIG. 1(c)). Thereafter, the clock pulse .phi..sub.1 having the "low" level is produced, and the signal charge stored under the transfer electrode 7 is permitted to flow into the floating diffusion layer 401 through a transfer channel under the output gate electrode 8 to which a predetermined constant voltage V.sub.OG is applied (FIG. 1(e)).
Here, the charge-to-voltage conversion is effected by the electrostatic capacity of the floating diffusion layer 401 with respect to the substrate 1, by the capacity of the wiring connected to the floating diffusion layer 401 and by the electrostatic capacity with respect to the gate electrode, the impedance conversion is effected by a source follower circuit consisting of the MOS transistor Tr.sub.2 and the resistor R, and the output voltage is obtained from the output terminal V.sub.OUT.
A potential change .DELTA.V.sub.SO in the floating diffusion layer 401 due to the flow of electric charge is given by, ##EQU1## where Q is the amount of input electric charge, and C.sub.0 is the sum of electrostatic capacity of the floating diffusion layer 401 relative to the substrate 1, electrostatic capacity relative to the gate electrode, and capacity of the wiring connected to the source region 301.
However, the output stage of the above-mentioned conventional charge transfer device involves defects as described below.
That is, when the electric charge that flows into the floating diffusion layer 401 becomes greater than the height V.sub.SAT of the potential barrier of when the reset pulse .phi..sub.R has the "low" level as shown in FIGS. 2(a) and 2(b), the electric charge flows into the drain region 402 through a transfer channel under the gate electrode 403. Therefore, the potential change does not increase due to the potential barrier V.sub.SAT but is limited by the barrier V.sub.SAT. As shown in FIG. 3, therefore, if it is attempted to increase the sensitivity of the output stage by decreasing the electrostatic capacity C.sub.O, the dynamic range is narrowed. Conversely, if it is attempted to broaden the dynamic range by increasing the electrostatic capacity C.sub.0, the sensitivity decreases.